PCI-SIG released version 0.5 of the PCI-Express 7.0 specification to its members this week. This is the second draft version of the specification and the final call for PCI-SIG members to submit new features to the standard. The latest update on the development of the specification comes less than a year after PCI-SIG released its initial draft version 0.3 of the specification, which PCI-SIG used to reiterate that development of the new standard is still on track for a final version in 2025.
PCIe 7.0 is the next generation of computer interconnect technology designed to increase data transfer speeds per pin to 128 GT/s, twice as fast as PCIe 6.0’s 64 GT/s and four times faster than PCIe 5.0’s 32 GT/s. times. This will allow a 16-lane (x16) connection to simultaneously support 256 GB/sec of bandwidth in each direction (excluding encoding overhead). Such speeds will be very convenient for future data centers as well as artificial intelligence and high-performance computing applications that require faster data transfer rates, including network data transfer rates.
To achieve impressive data transfer rates, PCIe 7.0 doubles the bus frequency at the physical layer compared to PCIe 5.0 and 6.0. Otherwise, the standard retains pulse amplitude modulation with level four signaling (PAM4), 1b/1b FLIT mode encoding, and the forward error correction (FEC) technology already used in PCIe 6.0. In addition to this, PCI-SIG said the PCIe 7.0 specification also focuses on enhanced channel parameters and coverage as well as improved power efficiency.
Overall, the engineers behind the standard have their work cut out for them, given that PCIe 7.0 requires a doubling of the bus frequency at the physical layer, a major development that PCIe 6.0 sidesteps via PAM4 signaling. When it comes to improving data signals, nothing comes free, and with PCIe 7.0, PCI-SIG is back to hard-mode development, so to speak, as the physical layer needs to be improved again – this time to enable it to operate at around 30GHz. Still, it remains to be seen how much of the heavy lifting will be done by smart signaling (and retimers) and how much will be done by pure material improvements, such as thicker printed circuit boards (PCBs) and low-loss materials. observe.
The next major step for PCIe 7.0 is to finalize version 0.7 of the specification, which is considered a complete draft in which all aspects must be fully defined and the electrical specifications must be verified with test chips. No new features can be added after this iteration of the specification is released. PCIe 6.0 ultimately went through 4 major drafts of 0.3, 0.5, 0.7 and 0.9 before being finalized, so PCIe 7.0 is likely to be on the same track.
Once 2025 is finalized, it should take a few years for the first PCIe 7.0 hardware to hit store shelves. While development of the controller IP and initial hardware is already underway, the process goes well beyond the release of the final PCIe specification.